For many years, wire bonding has been the most preferred method to realize the making of electrical interconnections between electronic devices such as integrated circuits (ICs) and substrates on which the ICs are mounted. The basic process flow is shown in FIG. 1, which illustrates a typical wire bonding method using a bonding tool comprising a capillary 10. The capillary 10 guides a length of bonding wire 12 and is operative to connect the bonding wire 12 to bond pads of electronic devices.
First, an electrical flame-off (“EFO”) device 14 forms a free air ball (“FAB”) 16 at a tip of the bonding wire 12. The capillary 10 retracts the bonding wire 12 and pulls the FAB 16 to its opening, and then guides the FAB 16 to descend onto a first bond site comprising a first bond pad 18. Force and ultrasonic energy are applied for a predetermined time to convert the FAB 16 into a ball bond 20 between the bonding wire 12 and the bond pad 18. This process is known as ball bonding. The wire is then released and extended from the ball bond 20 by the capillary 10 to a required length, formed into a wire loop and then bonded to another bond site, which comprises a second bond pad 22. A wedge bond 24 is formed at the second bond pad 22 by a process known as wedge bonding. An electrical connection is thus formed between the first and second bond pads 18, 22.
Traditionally, gold wire has been used to conduct wire bonding. In recent years, wire bonding using copper wire has become popular due to its superior mechanical and electrical performance, and low cost. However, copper is harder than gold and is prone to work-hardening during the bonding process, which increases the likelihood of underpad damage to the bond pad where wire bonding is performed. Defects such as pad cracking, peeling and silicon cratering may result.
The bond pad structure of an IC chip may vary widely due to the different possible applications of IC devices. Presently, most IC chips are designed for gold wire bonding. When transitioning to copper wire bonding, many bondability issues such as non-stick on pad (“NSOP”), ball lift, pad lift or underpad damage may be encountered. For a wire bonder which otherwise demonstrates good bonding performance, bondability issues may often be caused (1) by sensitive bond pad designs of the ICs to be bonded, or (2) by wire bonding parameters that are not optimized.
For the bondability issues related to factor (1), the conventional solution is to evaluate the structure of the bond pad by SEM/EDX analysis of a cross-section of the bond pad. However, this solution has some drawbacks. For example, preparation of the sectioned bond pad sample is difficult and time-consuming, and the die structure may also vary with different cross-section positions. It would be advantageous to develop a method to evaluate the bond pad robustness more accurately and within a shorter time.
For the bondability issues related to factor (2), the conventional solution is to optimize the bonding parameters using many bonding cycles to determine the parameters that result in the best bonding result. This approach is time consuming, especially for wire bonding sensitive IC devices.
A prior art approach is disclosed in detail in U.S. Pat. No. 7,004,372 entitled “Method for Determining Optimum Bond Parameters when Bonding with a Wire Bonder” which discloses a method for determining optimized bonding parameters for a bond pad. The method involves carrying out a number of bonding cycles of n=1 to k, whereby a bond force FB and an ultrasonic variable PB, and if necessary, at least one further bond parameter GB are each varied in discrete steps within a predetermined range. For each bonding cycle n, after attaching the wire ball to the connection point of an IC chip, the following steps are carried out:                (a) Application of a predetermined bond force FB1;        (b) Movement of a capillary out of a bond position in a predetermined horizontal direction during which a current IB,n flowing through a drive that moves the capillary is monitored;        (c) Stopping the movement of the capillary as soon as the current IB,n decreases; and        (d) Determining the maximum current IB,n,max (FB,n, PB,n, GB,n) from the progression of the current IB,n(FB,n, PB,n, GB,n, t). Then the parameters (FB,n, PB,n, GB,n) from values IB,n,max are determined as optimum bond parameters. FB1 is the same for all the shear tests.        
The fundamental idea of the aforesaid approach is to evaluate ball shear strength using the maximum drive current when moving the capillary in a horizontal direction. However, this method still requires many bonding cycles for process optimization. It requires a lot of manpower and cost to perform the bonding process optimization before the IC chips and substrates with the said bond pads may be put into production. Furthermore, this method may not be sensitive enough, especially for some bond pads that already have bond pad lift issues, since such bond pad lift is insensitive to shear load but sensitive to wire pull.